Hierarchy	Input	Constant Input	Unused Input	Floating Input	Output	Constant Output	Unused Output	Floating Output	Bidir	Constant Bidir	Unused Bidir	Input only Bidir	Output only Bidir
SRAM_inst|tristate_inst1[7]	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|tristate_inst1[6]	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|tristate_inst1[5]	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|tristate_inst1[4]	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|tristate_inst1[3]	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|tristate_inst1[2]	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|tristate_inst1[1]	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|tristate_inst1[0]	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|tristate_inst[7]	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|tristate_inst[6]	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|tristate_inst[5]	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|tristate_inst[4]	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|tristate_inst[3]	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|tristate_inst[2]	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|tristate_inst[1]	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|tristate_inst[0]	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]|MemoryCell_inst[7]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]|MemoryCell_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]|MemoryCell_inst[6]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]|MemoryCell_inst[6]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]|MemoryCell_inst[5]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]|MemoryCell_inst[5]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]|MemoryCell_inst[4]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]|MemoryCell_inst[4]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]|MemoryCell_inst[3]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]|MemoryCell_inst[3]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]|MemoryCell_inst[2]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]|MemoryCell_inst[2]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]|MemoryCell_inst[1]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]|MemoryCell_inst[1]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]|MemoryCell_inst[0]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]|MemoryCell_inst[0]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1023]	10	0	0	0	8	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]|MemoryCell_inst[7]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]|MemoryCell_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]|MemoryCell_inst[6]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]|MemoryCell_inst[6]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]|MemoryCell_inst[5]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]|MemoryCell_inst[5]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]|MemoryCell_inst[4]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]|MemoryCell_inst[4]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]|MemoryCell_inst[3]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]|MemoryCell_inst[3]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]|MemoryCell_inst[2]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]|MemoryCell_inst[2]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]|MemoryCell_inst[1]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]|MemoryCell_inst[1]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]|MemoryCell_inst[0]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]|MemoryCell_inst[0]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1022]	10	0	0	0	8	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]|MemoryCell_inst[7]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]|MemoryCell_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]|MemoryCell_inst[6]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]|MemoryCell_inst[6]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]|MemoryCell_inst[5]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]|MemoryCell_inst[5]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]|MemoryCell_inst[4]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]|MemoryCell_inst[4]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]|MemoryCell_inst[3]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]|MemoryCell_inst[3]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]|MemoryCell_inst[2]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]|MemoryCell_inst[2]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]|MemoryCell_inst[1]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]|MemoryCell_inst[1]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]|MemoryCell_inst[0]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]|MemoryCell_inst[0]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1021]	10	0	0	0	8	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]|MemoryCell_inst[7]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]|MemoryCell_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]|MemoryCell_inst[6]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]|MemoryCell_inst[6]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]|MemoryCell_inst[5]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]|MemoryCell_inst[5]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]|MemoryCell_inst[4]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]|MemoryCell_inst[4]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]|MemoryCell_inst[3]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]|MemoryCell_inst[3]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]|MemoryCell_inst[2]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]|MemoryCell_inst[2]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]|MemoryCell_inst[1]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]|MemoryCell_inst[1]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]|MemoryCell_inst[0]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]|MemoryCell_inst[0]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1020]	10	0	0	0	8	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]|MemoryCell_inst[7]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]|MemoryCell_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]|MemoryCell_inst[6]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]|MemoryCell_inst[6]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]|MemoryCell_inst[5]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]|MemoryCell_inst[5]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]|MemoryCell_inst[4]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]|MemoryCell_inst[4]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]|MemoryCell_inst[3]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]|MemoryCell_inst[3]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]|MemoryCell_inst[2]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]|MemoryCell_inst[2]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]|MemoryCell_inst[1]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]|MemoryCell_inst[1]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]|MemoryCell_inst[0]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]|MemoryCell_inst[0]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1019]	10	0	0	0	8	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]|MemoryCell_inst[7]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]|MemoryCell_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]|MemoryCell_inst[6]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]|MemoryCell_inst[6]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]|MemoryCell_inst[5]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]|MemoryCell_inst[5]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]|MemoryCell_inst[4]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]|MemoryCell_inst[4]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]|MemoryCell_inst[3]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]|MemoryCell_inst[3]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]|MemoryCell_inst[2]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]|MemoryCell_inst[2]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]|MemoryCell_inst[1]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]|MemoryCell_inst[1]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]|MemoryCell_inst[0]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]|MemoryCell_inst[0]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1018]	10	0	0	0	8	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]|MemoryCell_inst[7]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]|MemoryCell_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]|MemoryCell_inst[6]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]|MemoryCell_inst[6]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]|MemoryCell_inst[5]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]|MemoryCell_inst[5]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]|MemoryCell_inst[4]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]|MemoryCell_inst[4]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]|MemoryCell_inst[3]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]|MemoryCell_inst[3]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]|MemoryCell_inst[2]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]|MemoryCell_inst[2]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]|MemoryCell_inst[1]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]|MemoryCell_inst[1]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]|MemoryCell_inst[0]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]|MemoryCell_inst[0]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1017]	10	0	0	0	8	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]|MemoryCell_inst[7]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]|MemoryCell_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]|MemoryCell_inst[6]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]|MemoryCell_inst[6]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]|MemoryCell_inst[5]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]|MemoryCell_inst[5]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]|MemoryCell_inst[4]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]|MemoryCell_inst[4]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]|MemoryCell_inst[3]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]|MemoryCell_inst[3]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]|MemoryCell_inst[2]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]|MemoryCell_inst[2]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]|MemoryCell_inst[1]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]|MemoryCell_inst[1]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]|MemoryCell_inst[0]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]|MemoryCell_inst[0]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1016]	10	0	0	0	8	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1015]|MemoryCell_inst[7]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1015]|MemoryCell_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1015]|MemoryCell_inst[6]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1015]|MemoryCell_inst[6]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1015]|MemoryCell_inst[5]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1015]|MemoryCell_inst[5]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1015]|MemoryCell_inst[4]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1015]|MemoryCell_inst[4]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1015]|MemoryCell_inst[3]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1015]|MemoryCell_inst[3]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[1015]|MemoryCell_inst[2]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[1012]	10	0	0	0	8	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[1011]|MemoryCell_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[1011]	10	0	0	0	8	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[7]|MemoryCell_inst[0]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[7]	10	0	0	0	8	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[6]|MemoryCell_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[6]|MemoryCell_inst[6]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[6]|MemoryCell_inst[5]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[6]|MemoryCell_inst[3]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[6]|MemoryCell_inst[2]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[6]|MemoryCell_inst[1]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[6]|MemoryCell_inst[0]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[6]	10	0	0	0	8	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[5]|MemoryCell_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[5]|MemoryCell_inst[6]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[5]|MemoryCell_inst[6]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[5]|MemoryCell_inst[5]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[5]|MemoryCell_inst[5]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[5]|MemoryCell_inst[4]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[5]|MemoryCell_inst[3]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[5]|MemoryCell_inst[2]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[5]|MemoryCell_inst[1]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[5]|MemoryCell_inst[0]|D_latch_inst	2	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[5]|MemoryCell_inst[0]	3	0	0	0	1	0	0	0	0	0	0	0	0
SRAM_inst|word_inst[5]	10	0	0	0	8	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[4]|MemoryCell_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[4]|MemoryCell_inst[6]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[4]|MemoryCell_inst[5]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[4]|MemoryCell_inst[4]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[4]|MemoryCell_inst[2]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[4]|MemoryCell_inst[1]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[4]|MemoryCell_inst[0]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[3]|MemoryCell_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|word_inst[3]|MemoryCell_inst[6]	3	0	0	0	1	0	0	0	0	0	0	0	0
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SRAM_inst|dec_inst|dec0[9]	6	0	0	0	32	0	0	0	0	0	0	0	0
SRAM_inst|dec_inst|dec0[8]	6	0	0	0	32	0	0	0	0	0	0	0	0
SRAM_inst|dec_inst|dec0[7]	6	0	0	0	32	0	0	0	0	0	0	0	0
SRAM_inst|dec_inst|dec0[6]	6	0	0	0	32	0	0	0	0	0	0	0	0
SRAM_inst|dec_inst|dec0[5]	6	0	0	0	32	0	0	0	0	0	0	0	0
SRAM_inst|dec_inst|dec0[4]	6	0	0	0	32	0	0	0	0	0	0	0	0
SRAM_inst|dec_inst|dec0[3]	6	0	0	0	32	0	0	0	0	0	0	0	0
SRAM_inst|dec_inst|dec0[2]	6	0	0	0	32	0	0	0	0	0	0	0	0
SRAM_inst|dec_inst|dec0[1]	6	0	0	0	32	0	0	0	0	0	0	0	0
SRAM_inst|dec_inst|dec0[0]	6	0	0	0	32	0	0	0	0	0	0	0	0
SRAM_inst|dec_inst	11	1	0	1	1024	1	1	1	0	0	0	0	0
SRAM_inst	12	0	0	0	0	0	0	0	8	0	0	0	0
selector_inst|mux2_1_inst[9]	3	0	0	0	1	0	0	0	0	0	0	0	0
selector_inst|mux2_1_inst[8]	3	0	0	0	1	0	0	0	0	0	0	0	0
selector_inst|mux2_1_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
selector_inst|mux2_1_inst[6]	3	0	0	0	1	0	0	0	0	0	0	0	0
selector_inst|mux2_1_inst[5]	3	0	0	0	1	0	0	0	0	0	0	0	0
selector_inst|mux2_1_inst[4]	3	0	0	0	1	0	0	0	0	0	0	0	0
selector_inst|mux2_1_inst[3]	3	0	0	0	1	0	0	0	0	0	0	0	0
selector_inst|mux2_1_inst[2]	3	0	0	0	1	0	0	0	0	0	0	0	0
selector_inst|mux2_1_inst[1]	3	0	0	0	1	0	0	0	0	0	0	0	0
selector_inst|mux2_1_inst[0]	3	0	0	0	1	0	0	0	0	0	0	0	0
selector_inst	21	0	0	0	10	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|FullAdder_inst[9]	3	0	0	0	2	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|FullAdder_inst[8]	3	0	0	0	2	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|FullAdder_inst[7]	3	0	0	0	2	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|FullAdder_inst[6]	3	0	0	0	2	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|FullAdder_inst[5]	3	0	0	0	2	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|FullAdder_inst[4]	3	0	0	0	2	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|FullAdder_inst[3]	3	0	0	0	2	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|FullAdder_inst[2]	3	0	0	0	2	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|FullAdder_inst[1]	3	0	0	0	2	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|FullAdder_inst[0]	3	0	0	0	2	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|_xor[9]	2	0	0	0	1	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|_xor[8]	2	0	0	0	1	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|_xor[7]	2	0	0	0	1	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|_xor[6]	2	0	0	0	1	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|_xor[5]	2	0	0	0	1	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|_xor[4]	2	0	0	0	1	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|_xor[3]	2	0	0	0	1	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|_xor[2]	2	0	0	0	1	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|_xor[1]	2	0	0	0	1	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst|_xor[0]	2	0	0	0	1	0	0	0	0	0	0	0	0
Comparator_inst|FAS_inst	21	1	0	1	10	1	1	1	0	0	0	0	0
Comparator_inst	20	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|D_ff_inst[10]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|D_ff_inst[9]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|D_ff_inst[8]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|D_ff_inst[7]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|D_ff_inst[6]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|D_ff_inst[5]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|D_ff_inst[4]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|D_ff_inst[3]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|D_ff_inst[2]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|D_ff_inst[1]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|D_ff_inst[0]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|mux_inst[10]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|mux_inst[9]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|mux_inst[8]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|mux_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|mux_inst[6]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|mux_inst[5]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|mux_inst[4]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|mux_inst[3]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|mux_inst[2]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|mux_inst[1]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|mux_inst[0]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_back|HAS_inst[10]	3	1	0	1	2	1	1	1	0	0	0	0	0
Counter_back|HAS_inst[9]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_back|HAS_inst[8]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_back|HAS_inst[7]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_back|HAS_inst[6]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_back|HAS_inst[5]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_back|HAS_inst[4]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_back|HAS_inst[3]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_back|HAS_inst[2]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_back|HAS_inst[1]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_back|HAS_inst[0]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_back	15	12	0	12	11	12	12	12	0	0	0	0	0
Counter_front|D_ff_inst[10]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|D_ff_inst[9]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|D_ff_inst[8]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|D_ff_inst[7]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|D_ff_inst[6]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|D_ff_inst[5]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|D_ff_inst[4]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|D_ff_inst[3]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|D_ff_inst[2]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|D_ff_inst[1]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|D_ff_inst[0]	2	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|mux_inst[10]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|mux_inst[9]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|mux_inst[8]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|mux_inst[7]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|mux_inst[6]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|mux_inst[5]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|mux_inst[4]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|mux_inst[3]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|mux_inst[2]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|mux_inst[1]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|mux_inst[0]	3	0	0	0	1	0	0	0	0	0	0	0	0
Counter_front|HAS_inst[10]	3	1	0	1	2	1	1	1	0	0	0	0	0
Counter_front|HAS_inst[9]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_front|HAS_inst[8]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_front|HAS_inst[7]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_front|HAS_inst[6]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_front|HAS_inst[5]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_front|HAS_inst[4]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_front|HAS_inst[3]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_front|HAS_inst[2]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_front|HAS_inst[1]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_front|HAS_inst[0]	3	0	0	0	2	0	0	0	0	0	0	0	0
Counter_front	15	12	0	12	11	12	12	12	0	0	0	0	0